Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2003 by Hewlett-Packard Company.  All rights reserved.
       3             :  *
       4             :  * Permission is hereby granted, free of charge, to any person obtaining a copy
       5             :  * of this software and associated documentation files (the "Software"), to deal
       6             :  * in the Software without restriction, including without limitation the rights
       7             :  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
       8             :  * copies of the Software, and to permit persons to whom the Software is
       9             :  * furnished to do so, subject to the following conditions:
      10             :  *
      11             :  * The above copyright notice and this permission notice shall be included in
      12             :  * all copies or substantial portions of the Software.
      13             :  *
      14             :  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
      15             :  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
      16             :  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
      17             :  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
      18             :  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
      19             :  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
      20             :  * SOFTWARE.
      21             :  */
      22             : 
      23             : /*
      24             :  * These are common definitions for architectures that provide processor
      25             :  * ordered memory operations except that a later read may pass an
      26             :  * earlier write.  Real x86 implementations seem to be in this category,
      27             :  * except apparently for some IDT WinChips, which we ignore.
      28             :  */
      29             : 
      30             : #include "read_ordered.h"
      31             : 
      32             : AO_INLINE void
      33       92960 : AO_nop_write(void)
      34             : {
      35             :   /* AO_nop_write implementation is the same as of AO_nop_read. */
      36       92960 :   AO_compiler_barrier();
      37             :   /* sfence according to Intel docs.  Pentium 3 and up. */
      38             :   /* Unnecessary for cached accesses?                   */
      39       92961 : }
      40             : #define AO_HAVE_nop_write
      41             : 
      42             : #include "loadstore/ordered_stores_only.h"