25 #ifndef _JIT_COMPILER2_MACHINEOPERAND
26 #define _JIT_COMPILER2_MACHINEOPERAND
48 class StackSlotManager;
53 class ManagedStackSlot;
58 class MachineOperandDesc;
106 :
id(id_counter++), op_id(op_id), type(type), embedded_operands() {}
111 virtual const char* get_name()
const = 0;
130 bool is_stackslot()
const {
return is_StackSlot() || is_ManagedStackSlot(); }
135 if (id_base() != MO.
id_base()) {
136 return id_base() < MO.
id_base();
138 return id_offset()+id_size() <= MO.
id_offset();
158 return embedded_operands.size();
161 assert(i < embedded_operands.size());
162 return embedded_operands[
i];
165 assert(
i < embedded_operands.size());
166 return embedded_operands[
i];
169 assert(
i < embedded_operands.size());
170 return embedded_operands[
i];
173 return embedded_operands.begin();
176 return embedded_operands.end();
186 return embedded_operands.front();
189 return embedded_operands.back();
192 return embedded_operands.begin();
195 return embedded_operands.end();
199 return OS << get_name() ;
207 return "VoidOperand";
213 class VirtualRegister;
214 class MachineRegister;
215 class MachineAddress;
236 return "UnassignedReg";
247 vreg(vreg_counter++) {}
254 return MachineOperand::print(OS) << get_id();
275 return MachineOperand::print(OS) << get_index();
292 return "ManagedStackSlot";
297 return MachineOperand::print(OS) << get_id();
340 assert(get_type() == Type::IntTypeID);
344 assert(get_type() == Type::LongTypeID);
348 assert(get_type() == Type::FloatTypeID);
352 assert(get_type() == Type::DoubleTypeID);
371 class MachineOperandType {
375 REGISTER_VALUE = 1<<0,
378 ABSOLUTE_ADDR = 1<<3,
382 ALL = REGISTER_VALUE | REGISTER_MEM | IMMEDIATE | ABSOLUTE_ADDR | PIC_ADDR | PC_REL_ADDR
388 MachineOperandType() {
391 MachineOperandType(
unsigned t) {
395 MachineOperandType(
const MachineOperandType &MO) {
399 MachineOperandType& operator=(
const MachineOperandType &rhs) {
403 bool takes(
const TYPE t)
const {
406 unsigned get_type()
const {
409 void set_type(
unsigned t) {
418 OStream&
operator<<(OStream &
OS,
const MachineOperandType &MO);
425 return OS <<
"(MachineOperand) NULL";
455 struct less<cacao::jit::compiler2::MachineOperand*> {
464 struct equal_to<cacao::jit::compiler2::MachineOperand*> {
EmbeddedMachineOperand & operator[](std::size_t i)
embedded_operand_list::iterator operand_iterator
EmbeddedMachineOperand & back()
virtual const char * get_name() const
bool is_MachineOperand() const
bool is_stackslot() const
std::size_t op_size() const
virtual const char * get_name() const
virtual OStream & print(OStream &OS) const
virtual IdentifyTy id_base() const
OperandID get_OperandID() const
static unsigned vreg_counter
virtual ManagedStackSlot * to_ManagedStackSlot()
virtual OStream & print(OStream &OS) const
Custom new/delete handler mixin.
const_operand_iterator end() const
bool aquivalence_less(const MachineOperand &MO) const
virtual Register * to_Register()
bool is_StackSlot() const
virtual ~MachineOperand()
virtual ManagedStackSlot * to_ManagedStackSlot()
Descriptor of a MachineOperand.
bool operator()(cacao::jit::compiler2::MachineOperand *lhs, cacao::jit::compiler2::MachineOperand *rhs) const
virtual VoidOperand * to_VoidOperand()
virtual UnassignedReg * to_UnassignedReg()
virtual VirtualRegister * to_VirtualRegister()
Register(Type::TypeID type)
virtual OStream & print(OStream &OS) const
virtual const char * get_name() const
alloc::vector< EmbeddedMachineOperand >::type embedded_operand_list
virtual Register * to_Register()
std::list< T, Allocator< T > > type
operand_iterator find(MachineOperand *op)
virtual Address * to_Address()
std::size_t IdentifyOffsetTy
virtual bool is_virtual() const
True if operand is virtual and must be assigned during register allocation.
MachineOperand(OperandID op_id, Type::TypeID type)
std::vector< T, Allocator< T > > type
Simple stream class for formatted output.
virtual VirtualRegister * to_VirtualRegister()
virtual const char * get_name() const
virtual bool is_virtual() const
True if operand is virtual and must be assigned during register allocation.
VirtualRegister(Type::TypeID type)
virtual VoidOperand * to_VoidOperand()
bool has_embedded_operands()
virtual MachineRegister * to_MachineRegister()
alloc::list< MachineOperand * >::type OperandFile
embedded_operand_list::const_iterator const_operand_iterator
StackSlot(int index, Type::TypeID type)
bool is_VoidOperand() const
std::size_t operator()(cacao::jit::compiler2::MachineOperand *v) const
OStream & operator<<(OStream &OS, const std::string &t)
virtual bool needs_allocation() const
Return true if operand is processed during register allocation.
virtual Immediate * to_Immediate()
static std::size_t id_counter
bool aquivalent(const MachineOperand &MO) const
std::size_t IdentifySizeTy
Type::TypeID get_type() const
virtual const char * get_name() const
StackSlotManager * parent
virtual const char * get_name() const
Operands that can be directly used by the machine (register, memory, stackslot)
EmbeddedMachineOperand(MachineOperand *op)
MachineOperandDesc * real
std::size_t get_id() const
virtual StackSlot * to_StackSlot()
bool is_ManagedStackSlot() const
virtual IdentifyOffsetTy id_offset() const
bool operator()(MachineOperand *lhs, MachineOperand *rhs) const
embedded_operand_list embedded_operands
TODO describe.
virtual StackSlot * to_StackSlot()
int index
index of the stackslot
virtual Address * to_Address()
const_operand_iterator begin() const
virtual bool needs_allocation() const
Return true if operand is processed during register allocation.
virtual IdentifySizeTy id_size() const
bool is_Immediate() const
virtual MachineOperand * to_MachineOperand()
virtual OStream & print(OStream &OS) const
EmbeddedMachineOperand & front()
virtual const char * get_name() const
virtual UnassignedReg * to_UnassignedReg()
ManagedStackSlot(StackSlotManager *SSM, unsigned id, Type::TypeID type)
UnassignedReg(Type::TypeID type)