214 int32_t
s1,
s2,
s3, d = 0;
357 }
else if ((iptr->
sx.
val.
i > -256) && (iptr->
sx.
val.
i < 0)) {
492 bte = iptr->
sx.
s23.s3.bte;
513 bte = iptr->
sx.
s23.s3.bte;
529 if (iptr->
sx.
val.
i <= 15) {
675 }
else if (iptr->
sx.
val.
i == 0xffff) {
677 }
else if (iptr->
sx.
val.
i == 0xffffff) {
700 }
else if (iptr->
sx.
val.
i == 0xffff) {
705 }
else if (iptr->
sx.
val.
i == 0xffffff) {
728 }
else if (iptr->
sx.
val.
l == 0xffffL) {
730 }
else if (iptr->
sx.
val.
l == 0xffffffL) {
732 }
else if (iptr->
sx.
val.
l == 0xffffffffL) {
734 }
else if (iptr->
sx.
val.
l == 0xffffffffffL) {
736 }
else if (iptr->
sx.
val.
l == 0xffffffffffffL) {
738 }
else if (iptr->
sx.
val.
l == 0xffffffffffffffL) {
761 }
else if (iptr->
sx.
val.
l == 0xffffL) {
766 }
else if (iptr->
sx.
val.
l == 0xffffffL) {
771 }
else if (iptr->
sx.
val.
l == 0xffffffffL) {
776 }
else if (iptr->
sx.
val.
l == 0xffffffffffL) {
781 }
else if (iptr->
sx.
val.
l == 0xffffffffffffL) {
786 }
else if (iptr->
sx.
val.
l == 0xffffffffffffffL) {
914 if (d == s1 || d == s2) {
930 if (d == s1 || d == s2) {
946 if (d == s1 || d == s2) {
962 if (d == s1 || d == s2) {
978 if (d == s1 || d == s2) {
994 if (d == s1 || d == s2) {
1010 if (d == s1 || d == s2) {
1026 if (d == s1 || d == s2) {
1507 uf = iptr->
sx.
s23.s3.uf;
1514 fi = iptr->
sx.
s23.s3.fmiref->p.field;
1515 fieldtype = fi->
type;
1524 switch (fieldtype) {
1549 uf = iptr->
sx.
s23.s3.uf;
1556 fi = iptr->
sx.
s23.s3.fmiref->p.field;
1557 fieldtype = fi->
type;
1562 switch (fieldtype) {
1592 uf = iptr->
sx.
s23.s3.uf;
1598 fi = iptr->
sx.
s23.s3.fmiref->p.field;
1599 fieldtype = fi->
type;
1612 switch (fieldtype) {
1614 M_IST(s2, s1, disp);
1617 M_LST(s2, s1, disp);
1620 M_AST(s2, s1, disp);
1623 M_FST(s2, s1, disp);
1626 M_DST(s2, s1, disp);
1638 uf = iptr->
sx.
s23.s3.uf;
1645 fi = iptr->
sx.
s23.s3.fmiref->p.field;
1646 fieldtype = fi->
type;
1651 switch (fieldtype) {
1754 emit_beqz(cd, iptr->
dst.
block, s1);
1770 emit_bltz(cd, iptr->
dst.
block, s1);
1786 emit_blez(cd, iptr->
dst.
block, s1);
1802 emit_bnez(cd, iptr->
dst.
block, s1);
1818 emit_bgtz(cd, iptr->
dst.
block, s1);
1834 emit_bgez(cd, iptr->
dst.
block, s1);
1907 l = iptr->
sx.
s23.s2.tablelow;
1908 i = iptr->
sx.
s23.s3.tablehigh;
1913 }
else if (l <= 32768) {
1952 bte = iptr->
sx.
s23.s3.bte;
1953 if (bte->
stub == NULL)
1971 um = iptr->
sx.
s23.s3.um;
1978 lm = iptr->
sx.
s23.s3.fmiref->p.method;
1991 um = iptr->
sx.
s23.s3.um;
1997 lm = iptr->
sx.
s23.s3.fmiref->p.method;
2013 um = iptr->
sx.
s23.s3.um;
2020 lm = iptr->
sx.
s23.s3.fmiref->p.method;
2050 super = iptr->
sx.
s23.s3.c.cls;
2051 superindex = super->
index;
2058 if (super == NULL) {
2064 iptr->
sx.
s23.s3.c.ref,
2077 if (super == NULL) {
2080 iptr->
sx.
s23.s3.c.ref,
2106 if (super == NULL) {
2113 iptr->
sx.
s23.s3.c.ref,
2125 if (super == NULL || super->
vftbl->subtype_depth >= DISPLAY_SIZE) {
2132 if (super == NULL) {
2173 if (super == NULL) {
2191 iptr->
sx.
s23.s3.c.ref,
2227 super = iptr->
sx.
s23.s3.c.cls;
2228 superindex = super->
index;
2229 supervftbl = super->
vftbl;
2242 if (super == NULL) {
2249 iptr->
sx.
s23.s3.c.ref, disp);
2262 if (super == NULL) {
2270 iptr->
sx.
s23.s3.c.ref, 0);
2295 if (super == NULL) {
2301 iptr->
sx.
s23.s3.c.ref,
2314 if (super == NULL || super->
vftbl->subtype_depth >= DISPLAY_SIZE) {
2324 if (super == NULL) {
2363 if (super == NULL) {
2380 var =
VAR(iptr->
sx.
s23.s2.args[s1]);
2402 iptr->
sx.
s23.s3.c.ref,
2432 vm_abort(
"Unknown ICMD %d during code generation", iptr->
opc);
2487 #if defined(ENABLE_GC_CACAO)
2565 for (i = md->
paramcount - 1, j = i + skipparams; i >= 0; i--, j--) {
2689 #if defined(ENABLE_GC_CACAO)
void codegen_emit_instruction(jitdata *jd, instruction *iptr)
Generates machine code for one ICMD.
s4 dseg_add_double(codegendata *cd, double value)
#define M_BLDU(a, b, disp)
#define BUILTIN_FAST_canstore
#define PATCHER_resolve_classref_to_flags
s4 emit_load_s3(jitdata *jd, instruction *iptr, s4 tempreg)
#define M_LMUL_IMM(a, b, c)
s4 emit_load_s1(jitdata *jd, instruction *iptr, s4 tempreg)
#define M_CMOVGE(a, b, c)
#define M_ALD(a, b, disp)
#define PATCHER_invokeinterface
#define M_LST(a, b, disp)
#define M_ILD(a, b, disp)
s4 dseg_add_unique_address(codegendata *cd, void *value)
#define PATCHER_resolve_classref_to_vftbl
#define BUILTIN_multianewarray
#define IS_INT_LNG_TYPE(a)
#define M_IST(a, b, disp)
#define M_LDA(a, b, disp)
#define PATCHER_get_putfield
s4 dseg_add_address(codegendata *cd, void *value)
#define M_OR_IMM(a, b, c)
s4 dseg_add_unique_double(codegendata *cd, double value)
#define M_CMPULE_IMM(a, b, c)
#define dseg_add_functionptr(cd, value)
void codegen_emit_stub_native(jitdata *jd, methoddesc *nmd, functionptr f, int skipparams)
#define M_CMPLE_IMM(a, b, c)
typedef void(JNICALL *jvmtiEventSingleStep)(jvmtiEnv *jvmti_env
void emit_arraystore_check(codegendata *cd, instruction *iptr)
#define M_FST(a, b, disp)
patchref_t * patcher_add_patch_ref(jitdata *jd, functionptr patcher, void *ref, s4 disp)
#define M_FLD(a, b, disp)
void dseg_add_target(codegendata *cd, basicblock *target)
#define M_CMPULE(a, b, c)
java_object_t * codegen_finish_native_call(u1 *sp, u1 *pv)
const s4 abi_registers_integer_saved[]
#define PATCHER_get_putstatic
static int code_is_leafmethod(codeinfo *code)
#define BUILTIN_arraycheckcast
s4 dseg_add_s4(codegendata *cd, s4 value)
void vm_abort(const char *text,...)
void(* functionptr)(void)
#define M_SAADDQ(a, b, c)
java_handle_t * codegen_start_native_call(u1 *sp, u1 *pv)
#define PATCHER_instanceof_interface
#define IS_2_WORD_TYPE(a)
void emit_exception_check(codegendata *cd, instruction *iptr)
s4 codegen_reg_of_dst(jitdata *jd, instruction *iptr, s4 tempregnum)
#define M_CMPULT(a, b, c)
#define M_ISUB_IMM(a, b, c)
#define M_XOR_IMM(a, b, c)
#define M_FCMPEQS(a, b, c)
#define M_SST(a, b, disp)
constant_FMIref * fieldref
void emit_label_br(codegendata *cd, s4 label)
#define M_LST_U(a, b, disp)
s4 emit_load_s2(jitdata *jd, instruction *iptr, s4 tempreg)
#define M_ALD_INTERN(a, b, disp)
#define M_CMPLT_IMM(a, b, c)
#define M_ASUB_IMM(a, b, c)
#define M_SRL_IMM(a, b, c)
s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
s4 dseg_add_unique_s4(codegendata *cd, s4 value)
#define M_LLD_U(a, b, disp)
#define M_ZAPNOT_IMM(a, b, c)
#define M_AST(a, b, disp)
union instruction::@12 sx
void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
#define M_S8ADDQ(a, b, c)
#define PATCHER_checkcast_interface
#define M_LSUB_IMM(a, b, c)
void emit_store_dst(jitdata *jd, instruction *iptr, s4 d)
#define M_LADD_IMM(a, b, c)
#define PATCHER_invokestatic_special
#define M_BST(a, b, disp)
#define M_SRA_IMM(a, b, c)
#define M_FBEQZ(fa, disp)
#define M_AND_IMM(a, b, c)
#define PATCHER_invokevirtual
#define M_SLL_IMM(a, b, c)
#define M_IMUL_IMM(a, b, c)
static bool IS_INMEMORY(s4 flags)
void codegen_emit_epilog(jitdata *jd)
Generates machine code for the method epilog.
void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
#define M_CMPEQ_IMM(a, b, c)
static bool class_is_or_almost_initialized(classinfo *c)
#define PATCHER_initialize_class
#define M_S4ADDQ(a, b, c)
#define M_DST(a, b, disp)
#define INSTRUCTION_IS_UNRESOLVED(iptr)
struct instruction::@12::@13 s23
void codegen_emit_prolog(jitdata *jd)
Generates machine code for the method prolog.
#define M_LLD(a, b, disp)
const parseddesc_t parseddesc
static void emit_fmove(codegendata *cd, int s, int d)
Generates a float-move from register s to d.
#define PATCHER_resolve_classref_to_classinfo
void emit_label(codegendata *cd, s4 label)
#define M_SLDU(a, b, disp)
#define M_IADD_IMM(a, b, c)
void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
#define M_FCMPLTS(a, b, c)
#define M_DLD(a, b, disp)
s4 dseg_add_float(codegendata *cd, float value)
void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
static VM * get_current()