CACAO
codegen.hpp
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1 /* src/vm/jit/powerpc64/codegen.hpp - code generation macros and
2  definitions for PowerPC64
3 
4  Copyright (C) 1996-2013
5  CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 
7  This file is part of CACAO.
8 
9  This program is free software; you can redistribute it and/or
10  modify it under the terms of the GNU General Public License as
11  published by the Free Software Foundation; either version 2, or (at
12  your option) any later version.
13 
14  This program is distributed in the hope that it will be useful, but
15  WITHOUT ANY WARRANTY; without even the implied warranty of
16  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17  General Public License for more details.
18 
19  You should have received a copy of the GNU General Public License
20  along with this program; if not, write to the Free Software
21  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22  02110-1301, USA.
23 
24 */
25 
26 
27 #ifndef CODEGEN_HPP_
28 #define CODEGEN_HPP_ 1
29 
30 #include "config.h"
31 
32 #include "md-abi.hpp"
33 
34 #include "vm/global.hpp"
35 #include "vm/jit/jit.hpp"
36 #include "vm/jit/reg.hpp"
37 
38 
39 /* additional functions and macros to generate code ***************************/
40 
41 /* MCODECHECK(icnt) */
42 
43 #define MCODECHECK(icnt) \
44  do { \
45  if ((cd->mcodeptr + (icnt) * 4) > cd->mcodeend) \
46  codegen_increase(cd); \
47  } while (0)
48 
49 
50 #define ICONST(d,c) emit_iconst(cd, (d), (c))
51 #define LCONST(reg,c) emit_lconst(cd, (reg), (c))
52 
53 
54 #define ALIGNCODENOP \
55  if ((s4) ((ptrint) cd->mcodeptr & 7)) { \
56  M_NOP; \
57  }
58 
59 
60 /* branch defines *************************************************************/
61 /* and additional branch is needed when generating long branches */
62 #define BRANCH_NOPS \
63  do { \
64  if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {\
65  M_NOP; \
66  } \
67  M_NOP; \
68  } while (0)
69 
70 
71 /* patcher defines ************************************************************/
72 
73 #define PATCHER_CALL_SIZE 1 * 4 /* an instruction is 4-bytes long */
74 
75 #define PATCHER_NOPS \
76  do { \
77  M_NOP; \
78  } while (0)
79 
80 
81 /* macros to create code ******************************************************/
82 
83 #define M_OP3(opcode,y,oe,rc,d,a,b) \
84  do { \
85  *((u4 *) cd->mcodeptr) = (((opcode) << 26) | ((d) << 21) | ((a) << 16) | ((b) << 11) | ((oe) << 10) | ((y) << 1) | (rc)); \
86  cd->mcodeptr += 4; \
87  } while (0)
88 
89 #define M_OP4(x,y,rc,d,a,b,c) \
90  do { \
91  *((u4 *) cd->mcodeptr) = (((x) << 26) | ((d) << 21) | ((a) << 16) | ((b) << 11) | ((c) << 6) | ((y) << 1) | (rc)); \
92  cd->mcodeptr += 4; \
93  } while (0)
94 
95 #define M_OP2_IMM(x,d,a,i) \
96  do { \
97  *((u4 *) cd->mcodeptr) = (((x) << 26) | ((d) << 21) | ((a) << 16) | ((i) & 0xffff)); \
98  cd->mcodeptr += 4; \
99  } while (0)
100 
101 /* for instruction decodeing */
102 #define M_INSTR_OP2_IMM_D(x) (((x) >> 21) & 0x1f )
103 #define M_INSTR_OP2_IMM_A(x) (((x) >> 16) & 0x1f )
104 #define M_INSTR_OP2_IMM_I(x) ( (x) & 0xffff)
105 
106 #define M_BCMASK 0x0000fffc /* (((1 << 16) - 1) & ~3) */
107 #define M_BMASK 0x03fffffc /* (((1 << 26) - 1) & ~3) */
108 
109 #define M_B(x,i,a,l) \
110  do { \
111  *((u4 *) cd->mcodeptr) = (((x) << 26) | ((((i) * 4) + 4) & M_BMASK) | ((a) << 1) | (l)); \
112  cd->mcodeptr += 4; \
113  } while (0)
114 
115 #define M_BC(x,bo,bi,i,a,l) \
116  do { \
117  *((u4 *) cd->mcodeptr) = (((x) << 26) | ((bo) << 21) | ((bi) << 16) | (((i) * 4 + 4) & M_BCMASK) | ((a) << 1) | (l)); \
118  cd->mcodeptr += 4; \
119  } while (0)
120 
121 
122 
123 #define M_EXTSW(a,b) M_OP3(31, 986, 0, 0, a, b, 0)
124 
125 
126 /* instruction macros *********************************************************/
127 
128 #define M_ILLEGAL M_OP3(0, 0, 0, 0, 0, 0, 0)
129 #define M_IADD(a,b,c) M_LADD(a,b,c)
130 #define M_LADD(a,b,c) M_OP3(31, 266, 0, 0, c, a, b)
131 #define M_IADD_IMM(a,b,c) M_OP2_IMM(14, c, a, b) /* XXX */
132 #define M_LADD_IMM(a,b,c) M_OP2_IMM(14, c, a, b)
133 #define M_ADDC(a,b,c) M_OP3(31, 10, 0, 0, c, a, b)
134 #define M_ADDIC(a,b,c) M_OP2_IMM(12, c, a, b)
135 #define M_ADDICTST(a,b,c) M_OP2_IMM(13, c, a, b)
136 #define M_ADDE(a,b,c) M_OP3(31, 138, 0, 0, c, a, b)
137 #define M_ADDZE(a,b) M_OP3(31, 202, 0, 0, b, a, 0)
138 #define M_ADDME(a,b) M_OP3(31, 234, 0, 0, b, a, 0)
139 
140 #define M_SUB(a,b,c) M_OP3(31, 40, 0, 0, c, b, a)
141 #define M_ISUBTST(a,b,c) M_OP3(31, 40, 0, 1, c, b, a)
142 #define M_SUBC(a,b,c) M_OP3(31, 8, 0, 0, c, b, a)
143 #define M_SUBIC(a,b,c) M_OP2_IMM(8, c, b, a)
144 #define M_SUBE(a,b,c) M_OP3(31, 136, 0, 0, c, b, a)
145 #define M_SUBZE(a,b) M_OP3(31, 200, 0, 0, b, a, 0)
146 #define M_SUBME(a,b) M_OP3(31, 232, 0, 0, b, a, 0)
147 
148 #define M_AND(a,b,c) M_OP3(31, 28, 0, 0, a, c, b)
149 #define M_AND_IMM(a,b,c) M_OP2_IMM(28, a, c, b)
150 #define M_ANDIS(a,b,c) M_OP2_IMM(29, a, c, b)
151 #define M_OR(a,b,c) M_OP3(31, 444, 0, 0, a, c, b)
152 #define M_OR_TST(a,b,c) M_OP3(31, 444, 0, 1, a, c, b)
153 #define M_OR_IMM(a,b,c) M_OP2_IMM(24, a, c, b)
154 #define M_ORIS(a,b,c) M_OP2_IMM(25, a, c, b)
155 #define M_XOR(a,b,c) M_OP3(31, 316, 0, 0, a, c, b)
156 #define M_XOR_IMM(a,b,c) M_OP2_IMM(26, a, c, b)
157 #define M_XORIS(a,b,c) M_OP2_IMM(27, a, c, b)
158 
159 /* RLDICR is said to be turing complete, this seems right */
160 #define M_SLL(a,b,c) M_OP3(31, 27, 0, 0, a, c, b)
161 #define M_SLL_IMM(a,b,c) M_OP3(30, ((b)&0x20 ? 1:0), 0, ((((63-(b))&0x1f)<<6) | (((63-(b))&0x20 ? 1:0)<<5) | 0x04), a, c, (b)&0x1f);
162 #define M_SRL(a,b,c) M_OP3(31, 539, 0, 0, a, c, b)
163 #define M_SRL_IMM(a,b,c) M_OP3(30, ((64-(b))&0x20 ? 1:0), 0, (((((b))&0x1f)<<6) | ((((b))&0x20 ? 1:0)<<5) | 0x00), a, c, (64-(b))&0x1f);
164 #define M_SRA(a,b,c) M_OP3(31, 794, 0, 0, a, c, b)
165 #define M_SRA_IMM(a,b,c) M_OP3(31, (826 | ((b)&0x20?1:0)), 0, 0, a, c, ((b)&0x1f))
166 #define M_RLDICL(a,b,c,d) M_OP4(30, ((b)&0x20 ? 1:0), 0, a, d, (b)&0x1f, c)
167 #define M_CNTLZ(a,b) M_OP3(31, 58, 0, 0, a, b, 0)
168 
169 #define M_MUL(a,b,c) M_OP3(31, 233, 0, 0, c, a, b)
170 #define M_MUL_IMM(a,b,c) M_OP2_IMM(7, c, a, b)
171 #define M_DIV(a,b,c) M_OP3(31, 489, 1, 0, c, a, b)
172 
173 #define M_NEG(a,b) M_OP3(31, 104, 0, 0, b, a, 0)
174 #define M_NOT(a,b) M_OP3(31, 124, 0, 0, a, b, a)
175 
176 #define M_SUBFIC(a,b,c) M_OP2_IMM(8, c, a, b)
177 #define M_SUBFZE(a,b) M_OP3(31, 200, 0, 0, b, a, 0)
178 #define M_RLWINM(a,b,c,d,e) M_OP4(21, d, 0, a, e, b, c)
179 #define M_ADDZE(a,b) M_OP3(31, 202, 0, 0, b, a, 0)
180 #define M_ADDIS(a,b,c) M_OP2_IMM(15, c, a, b)
181 #define M_STFIWX(a,b,c) M_OP3(31, 983, 0, 0, a, b, c)
182 
183 #define M_LWAX(a,b,c) M_OP3(31, 341, 0, 0, a, b, c)
184 #define M_LHZX(a,b,c) M_OP3(31, 279, 0, 0, a, b, c)
185 #define M_LHAX(a,b,c) M_OP3(31, 343, 0, 0, a, b, c)
186 #define M_LHAX(a,b,c) M_OP3(31, 343, 0, 0, a, b, c)
187 #define M_LBZX(a,b,c) M_OP3(31, 87, 0, 0, a, b, c)
188 #define M_LFSX(a,b,c) M_OP3(31, 535, 0, 0, a, b, c)
189 #define M_LFDX(a,b,c) M_OP3(31, 599, 0, 0, a, b, c)
190 
191 #define M_STWX(a,b,c) M_OP3(31, 151, 0, 0, a, b, c)
192 #define M_STHX(a,b,c) M_OP3(31, 407, 0, 0, a, b, c)
193 #define M_STBX(a,b,c) M_OP3(31, 215, 0, 0, a, b, c)
194 #define M_STFSX(a,b,c) M_OP3(31, 663, 0, 0, a, b, c)
195 #define M_STFDX(a,b,c) M_OP3(31, 727, 0, 0, a, b, c)
196 
197 /*
198 #define M_STWU_INTERN(a,b,disp) M_OP2_IMM(37,a,b,disp)
199 #define M_STWU(a,b,disp) \
200  do { \
201  s4 lo = (disp) & 0x0000ffff; \
202  s4 hi = ((disp) >> 16); \
203  if (((disp) >= -32678) && ((disp) <= 32767)) { \
204  M_STWU_INTERN(a,b,lo); \
205  } else { \
206  M_ADDIS(REG_ZERO,hi,REG_ITMP3); \
207  M_OR_IMM(REG_ITMP3,lo,REG_ITMP3); \
208  M_STWUX(REG_SP,REG_SP,REG_ITMP3); \
209  } \
210  } while (0)
211 
212 #define M_STWUX(a,b,c) M_OP3(31,183,0,0,a,b,c)
213 */
214 
215 #define M_STDU_INTERN(a,b,disp) M_OP2_IMM(62,a,b,(disp)|0x0001)
216 #define M_STDU(a,b,disp) \
217  do { \
218  s4 lo = (disp) & 0x0000ffff; \
219  s4 hi = ((disp) >> 16); \
220  if (((disp) >= -32678) && ((disp) <= 32767)) { \
221  M_STDU_INTERN(a,b,lo); \
222  } else { \
223  M_ADDIS(REG_ZERO,hi,REG_ITMP3); \
224  M_OR_IMM(REG_ITMP3,lo,REG_ITMP3); \
225  M_STDUX(REG_SP,REG_SP,REG_ITMP3); \
226  } \
227  } while (0)
228 #define M_STDUX(a,b,c) M_OP3(31,181,0,0,a,b,c)
229 
230 #define M_LDAH(a,b,c) M_ADDIS(b, c, a)
231 #define M_TRAP M_OP3(31, 4, 0, 0, 31, 0, 0)
232 
233 #define M_NOP M_OR_IMM(0, 0, 0)
234 #define M_MOV(a,b) M_OR(a, a, b)
235 #define M_TST(a) M_OP3(31, 444, 0, 1, a, a, a)
236 
237 #define M_DADD(a,b,c) M_OP3(63, 21, 0, 0, c, a, b)
238 #define M_FADD(a,b,c) M_OP3(59, 21, 0, 0, c, a, b)
239 #define M_DSUB(a,b,c) M_OP3(63, 20, 0, 0, c, a, b)
240 #define M_FSUB(a,b,c) M_OP3(59, 20, 0, 0, c, a, b)
241 #define M_DMUL(a,b,c) M_OP4(63, 25, 0, c, a, 0, b)
242 #define M_FMUL(a,b,c) M_OP4(59, 25, 0, c, a, 0, b)
243 #define M_DDIV(a,b,c) M_OP3(63, 18, 0, 0, c, a, b)
244 #define M_FDIV(a,b,c) M_OP3(59, 18, 0, 0, c, a, b)
245 
246 #define M_FABS(a,b) M_OP3(63, 264, 0, 0, b, 0, a)
247 #define M_CVTDL(a,b) M_OP3(63, 14, 0, 0, b, 0, a)
248 #define M_CVTDL_C(a,b) M_OP3(63, 15, 0, 0, b, 0, a)
249 #define M_CVTDF(a,b) M_OP3(63, 12, 0, 0, b, 0, a)
250 #define M_FMOV(a,b) M_OP3(63, 72, 0, 0, b, 0, a)
251 #define M_FMOVN(a,b) M_OP3(63, 40, 0, 0, b, 0, a)
252 #define M_DSQRT(a,b) M_OP3(63, 22, 0, 0, b, 0, a)
253 #define M_FSQRT(a,b) M_OP3(59, 22, 0, 0, b, 0, a)
254 
255 #define M_FCMPU(a,b) M_OP3(63, 0, 0, 0, 0, a, b)
256 #define M_FCMPO(a,b) M_OP3(63, 32, 0, 0, 0, a, b)
257 
258 #define M_BLDU(a,b,c) M_OP2_IMM(34, a, b, c) /* LBZ */
259 #define M_SLDU(a,b,c) M_OP2_IMM(40, a, b, c) /* LHZ */
260 
261 #if 0
262 #define M_ILD_INTERN(a,b,disp) M_OP2_IMM(32,a,b,disp) /* LWZ */
263 #endif
264 
265 #define M_LWZ(a,b,disp) M_OP2_IMM(32,a,b,disp) /* needed for hardware exceptions */
266 
267 #define M_ILD_INTERN(a,b,disp) M_OP2_IMM(58, a, b, (((disp) & 0xfffe) | 0x0002)) /* this is LWA actually */
268 
269 #define M_ILD(a,b,disp) \
270  do { \
271  s4 lo = (short) (disp); \
272  s4 hi = (short) (((disp) - lo) >> 16); \
273  if (hi == 0) { \
274  M_ILD_INTERN(a,b,lo); \
275  } else { \
276  M_ADDIS(b,hi,a); \
277  M_ILD_INTERN(a,a,lo); \
278  } \
279  } while (0)
280 
281 #define M_LLD_INTERN(a,b,disp) M_OP2_IMM(58,a,b,disp) /* LD */
282 
283 #define M_LLD(a,b,disp) \
284  do { \
285  s4 lo = (short) (disp); \
286  s4 hi = (short) (((disp) - lo) >> 16); \
287  if (hi == 0) { \
288  M_LLD_INTERN(a,b,lo); \
289  } else { \
290  M_ADDIS(b,hi,a); \
291  M_LLD_INTERN(a,GET_LOW_REG(a),lo); \
292  } \
293  } while (0)
294 
295 #define M_ALD_INTERN(a,b,disp) M_LLD_INTERN(a,b,disp)
296 #define M_ALD(a,b,disp) M_LLD(a,b,disp)
297 #define M_ALD_DSEG(a,disp) M_LLD(a,REG_PV,disp)
298 #define M_ALDX(a,b,c) M_OP3(31, 21, 0, 0, a, b, c) /* LDX */
299 
300 #define M_BST(a,b,c) M_OP2_IMM(38, a, b, c) /* STB */
301 #define M_SST(a,b,c) M_OP2_IMM(44, a, b, c) /* LMW */
302 
303 #define M_IST_INTERN(a,b,disp) M_OP2_IMM(36,a,b,disp) /* STW */
304 
305 /* Stores with displacement overflow should only happen with PUTFIELD
306  or on the stack. The PUTFIELD instruction does not use REG_ITMP3
307  and a reg_of_var call should not use REG_ITMP3!!! */
308 
309 #define M_IST(a,b,disp) \
310  do { \
311  s4 lo = (short) (disp); \
312  s4 hi = (short) (((disp) - lo) >> 16); \
313  if (hi == 0) { \
314  M_IST_INTERN(a,b,lo); \
315  } else { \
316  M_ADDIS(b,hi,REG_ITMP3); \
317  M_IST_INTERN(a,REG_ITMP3,lo); \
318  } \
319  } while (0)
320 
321 #define M_LST_INTERN(a,b,disp) M_OP2_IMM(62,a,b,disp) /* STD */
322 
323 #define M_LST(a,b,disp) \
324  do { \
325  s4 lo = (short) (disp); \
326  s4 hi = (short) (((disp) - lo) >> 16); \
327  if (hi == 0) { \
328  M_LST_INTERN(a,b,lo); \
329  } else { \
330  M_ADDIS(b,hi,REG_ITMP3); \
331  M_LST_INTERN(a,REG_ITMP3, lo); \
332  } \
333  } while (0)
334 
335 #define M_AST_INTERN(a,b,disp) M_LST_INTERN(a,b,disp)
336 #define M_AST(a,b,disp) M_LST(a,b,disp)
337 #define M_ASTX(a,b,c) M_OP3(31, 149, 0, 0, a, b, c)
338 #define M_LSTX(a,b,c) M_ASTX(a,b,c)
339 
340 
341 #define M_BSEXT(a,b) M_OP3(31, 954, 0, 0, a, b, 0)
342 #define M_CZEXT(a,b) M_RLWINM(a,0,16,31,b)
343 #define M_SSEXT(a,b) M_OP3(31, 922, 0, 0, a, b, 0)
344 #define M_ISEXT(a,b) M_OP3(31, 986, 0, 0, a, b, 0)
345 
346 #define M_BR(a) M_B(18, a, 0, 0)
347 #define M_BL(a) M_B(18, a, 0, 1)
348 #define M_RET M_OP3(19, 16, 0, 0, 20, 0, 0)
349 #define M_JSR M_OP3(19, 528, 0, 1, 20, 0, 0)
350 #define M_RTS M_OP3(19, 528, 0, 0, 20, 0, 0)
351 
352 #define M_CMP(a,b) M_OP3(31, 0, 0, 0, 1, a, b)
353 #define M_CMPU(a,b) M_OP3(31, 32, 0, 0, 1, a, b)
354 #define M_CMPI(a,b) M_OP2_IMM(11, 1, a, b)
355 #define M_CMPUI(a,b) M_OP2_IMM(10, 1, a, b)
356 
357 #define M_BLT(a) M_BC(16, 12, 0, a, 0, 0)
358 #define M_BLE(a) M_BC(16, 4, 1, a, 0, 0)
359 #define M_BGT(a) M_BC(16, 12, 1, a, 0, 0)
360 #define M_BGE(a) M_BC(16, 4, 0, a, 0, 0)
361 #define M_BEQ(a) M_BC(16, 12, 2, a, 0, 0)
362 #define M_BNE(a) M_BC(16, 4, 2, a, 0, 0)
363 #define M_BNAN(a) M_BC(16, 12, 3, a, 0, 0)
364 
365 #define M_FLD_INTERN(a,b,disp) M_OP2_IMM(48,a,b,disp)
366 #define M_DLD_INTERN(a,b,disp) M_OP2_IMM(50,a,b,disp)
367 
368 #define M_FLD(a,b,disp) \
369  do { \
370  s4 lo = (short) (disp); \
371  s4 hi = (short) (((disp) - lo) >> 16); \
372  if (hi == 0) { \
373  M_FLD_INTERN(a,b,lo); \
374  } else { \
375  M_ADDIS(b,hi,REG_ITMP3); \
376  M_FLD_INTERN(a,REG_ITMP3,lo); \
377  } \
378  } while (0)
379 
380 #define M_DLD(a,b,disp) \
381  do { \
382  s4 lo = (short) (disp); \
383  s4 hi = (short) (((disp) - lo) >> 16); \
384  if (hi == 0) { \
385  M_DLD_INTERN(a,b,lo); \
386  } else { \
387  M_ADDIS(b,hi,REG_ITMP3); \
388  M_DLD_INTERN(a,REG_ITMP3,lo); \
389  } \
390  } while (0)
391 
392 #define M_FST_INTERN(a,b,disp) M_OP2_IMM(52,a,b,disp) /* STFS */
393 #define M_DST_INTERN(a,b,disp) M_OP2_IMM(54,a,b,disp) /* STFD */
394 
395 #define M_FST(a,b,disp) \
396  do { \
397  s4 lo = (short) (disp); \
398  s4 hi = (short) (((disp) - lo) >> 16); \
399  if (hi == 0) { \
400  M_FST_INTERN(a,b,lo); \
401  } else { \
402  M_ADDIS(b,hi,REG_ITMP3); \
403  M_FST_INTERN(a,REG_ITMP3,lo); \
404  } \
405  } while (0)
406 
407 #define M_DST(a,b,disp) \
408  do { \
409  s4 lo = (short) (disp); \
410  s4 hi = (short) (((disp) - lo) >> 16); \
411  if (hi == 0) { \
412  M_DST_INTERN(a,b,lo); \
413  } else { \
414  M_ADDIS(b,hi,REG_ITMP3); \
415  M_DST_INTERN(a,REG_ITMP3,lo); \
416  } \
417  } while (0)
418 
419 #define M_MFLR(a) M_OP3(31, 339, 0, 0, a, 8, 0)
420 #define M_MFXER(a) M_OP3(31, 339, 0, 0, a, 1, 0)
421 #define M_MFCTR(a) M_OP3(31, 339, 0, 0, a, 9, 0)
422 #define M_MTLR(a) M_OP3(31, 467, 0, 0, a, 8, 0)
423 #define M_MTXER(a) M_OP3(31, 467, 0, 0, a, 1, 0)
424 #define M_MTCTR(a) M_OP3(31, 467, 0, 0, a, 9, 0)
425 
426 #define M_LDA_INTERN(a,b,c) M_LADD_IMM(b, c, a)
427 
428 #define M_LDA(a,b,disp) \
429  do { \
430  s4 lo = (short) (disp); \
431  s4 hi = (short) (((disp) - lo) >> 16); \
432  if (hi == 0) { \
433  M_LDA_INTERN(a,b,lo); \
434  } else { \
435  M_ADDIS(b,hi,a); \
436  M_LDA_INTERN(a,a,lo); \
437  } \
438  } while (0)
439 
440 
441 #define M_LDATST(a,b,c) M_ADDICTST(b, c, a)
442 #define M_CLR(a) M_LADD_IMM(0, 0, a)
443 #define M_CLR_HIGH(a) M_OP3(30, 0, 0, 0x20, (a), (a), 0);
444 #define M_AADD_IMM(a,b,c) M_LADD_IMM(a, b, c)
445 
446 #define M_DMOV(a,b) M_FMOV(a,b)
447 
448 #define M_ACMP(a,b) M_CMP(a,b)
449 #define M_ICMP(a,b) M_CMP(a,b)
450 
451 #define M_TEST(a) M_TST(a)
452 
453 #endif // CODEGEN_HPP_
454 
455 
456 /*
457  * These are local overrides for various environment variables in Emacs.
458  * Please do not remove this and leave it at the end of the file, where
459  * Emacs will automagically detect them.
460  * ---------------------------------------------------------------------
461  * Local variables:
462  * mode: c++
463  * indent-tabs-mode: t
464  * c-basic-offset: 4
465  * tab-width: 4
466  * End:
467  */
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