Line data    Source code

       1             : /*
       2             :  * Copyright (c) 2003 by Hewlett-Packard Company.  All rights reserved.
       3             :  *
       4             :  * Permission is hereby granted, free of charge, to any person obtaining a copy
       5             :  * of this software and associated documentation files (the "Software"), to deal
       6             :  * in the Software without restriction, including without limitation the rights
       7             :  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
       8             :  * copies of the Software, and to permit persons to whom the Software is
       9             :  * furnished to do so, subject to the following conditions:
      10             :  *
      11             :  * The above copyright notice and this permission notice shall be included in
      12             :  * all copies or substantial portions of the Software.
      13             :  *
      14             :  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
      15             :  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
      16             :  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
      17             :  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
      18             :  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
      19             :  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
      20             :  * SOFTWARE.
      21             :  */
      22             : 
      23             : /*
      24             :  * These are common definitions for architectures that provide processor
      25             :  * ordered memory operations except that a later read may pass an
      26             :  * earlier write.  Real x86 implementations seem to be in this category,
      27             :  * except apparently for some IDT WinChips, which we ignore.
      28             :  */
      29             : 
      30             : #include "read_ordered.h"
      31             : 
      32             : AO_INLINE void
      33             : AO_nop_write(void)
      34             : {
      35             :   AO_compiler_barrier();
      36             :   /* sfence according to Intel docs.  Pentium 3 and up. */
      37             :   /* Unnecessary for cached accesses?                   */
      38             : }
      39             : #define AO_HAVE_nop_write
      40             : 
      41             : #if defined(AO_HAVE_store)
      42             :   AO_INLINE void
      43         252 :   AO_store_write(volatile AO_t *addr, AO_t val)
      44             :   {
      45         252 :     AO_compiler_barrier();
      46         252 :     AO_store(addr, val);
      47         252 :   }
      48             : # define AO_HAVE_store_write
      49             : 
      50             : # define AO_store_release(addr, val) AO_store_write(addr, val)
      51             : # define AO_HAVE_store_release
      52             : #endif /* AO_HAVE_store */
      53             : 
      54             : #if defined(AO_HAVE_char_store)
      55             :   AO_INLINE void
      56           0 :   AO_char_store_write(volatile unsigned char *addr, unsigned char val)
      57             :   {
      58           0 :     AO_compiler_barrier();
      59           0 :     AO_char_store(addr, val);
      60           0 :   }
      61             : # define AO_HAVE_char_store_write
      62             : 
      63             : # define AO_char_store_release(addr, val) AO_char_store_write(addr, val)
      64             : # define AO_HAVE_char_store_release
      65             : #endif /* AO_HAVE_char_store */
      66             : 
      67             : #if defined(AO_HAVE_short_store)
      68             :   AO_INLINE void
      69             :   AO_short_store_write(volatile unsigned short *addr, unsigned short val)
      70             :   {
      71             :     AO_compiler_barrier();
      72             :     AO_short_store(addr, val);
      73             :   }
      74             : # define AO_HAVE_short_store_write
      75             : 
      76             : # define AO_short_store_release(addr, val) AO_short_store_write(addr, val)
      77             : # define AO_HAVE_short_store_release
      78             : #endif /* AO_HAVE_short_store */
      79             : 
      80             : #if defined(AO_HAVE_int_store)
      81             :   AO_INLINE void
      82             :   AO_int_store_write(volatile unsigned int *addr, unsigned int val)
      83             :   {
      84             :     AO_compiler_barrier();
      85             :     AO_int_store(addr, val);
      86             :   }
      87             : # define AO_HAVE_int_store_write
      88             : 
      89             : # define AO_int_store_release(addr, val) AO_int_store_write(addr, val)
      90             : # define AO_HAVE_int_store_release
      91             : #endif /* AO_HAVE_int_store */