25 #ifndef _JIT_COMPILER2_MACHINEOPERAND
26 #define _JIT_COMPILER2_MACHINEOPERAND
47 class StackSlotManager;
52 class ManagedStackSlot;
57 class MachineOperandDesc;
105 :
id(id_counter++), op_id(op_id), type(type), embedded_operands() {}
110 virtual const char* get_name()
const = 0;
129 bool is_stackslot()
const {
return is_StackSlot() || is_ManagedStackSlot(); }
134 if (id_base() != MO.
id_base()) {
135 return id_base() < MO.
id_base();
137 return id_offset()+id_size() <= MO.
id_offset();
157 return embedded_operands.size();
160 assert(i < embedded_operands.size());
161 return embedded_operands[
i];
164 assert(
i < embedded_operands.size());
165 return embedded_operands[
i];
168 assert(
i < embedded_operands.size());
169 return embedded_operands[
i];
172 return embedded_operands.begin();
175 return embedded_operands.end();
185 return embedded_operands.front();
188 return embedded_operands.back();
191 return embedded_operands.begin();
194 return embedded_operands.end();
198 return OS << get_name() ;
206 return "VoidOperand";
212 class VirtualRegister;
213 class MachineRegister;
214 class MachineAddress;
235 return "UnassignedReg";
246 vreg(vreg_counter++) {}
253 return MachineOperand::print(OS) << get_id();
274 return MachineOperand::print(OS) << get_index();
329 return "ManagedStackSlot";
358 return MachineOperand::print(OS) << get_id();
409 assert(get_type() == Type::IntTypeID);
413 assert(get_type() == Type::LongTypeID);
417 assert(get_type() == Type::FloatTypeID);
421 assert(get_type() == Type::DoubleTypeID);
442 class MachineOperandType {
446 REGISTER_VALUE = 1<<0,
449 ABSOLUTE_ADDR = 1<<3,
453 ALL = REGISTER_VALUE | REGISTER_MEM | IMMEDIATE | ABSOLUTE_ADDR | PIC_ADDR | PC_REL_ADDR
459 MachineOperandType() {
462 MachineOperandType(
unsigned t) {
466 MachineOperandType(
const MachineOperandType &MO) {
470 MachineOperandType& operator=(
const MachineOperandType &rhs) {
474 bool takes(
const TYPE t)
const {
477 unsigned get_type()
const {
480 void set_type(
unsigned t) {
489 OStream&
operator<<(OStream &
OS,
const MachineOperandType &MO);
496 return OS <<
"(MachineOperand) NULL";
517 struct hash<cacao::jit::compiler2::MachineOperand*> {
524 struct less<cacao::jit::compiler2::MachineOperand*> {
533 struct equal_to<cacao::jit::compiler2::MachineOperand*> {
EmbeddedMachineOperand & operator[](std::size_t i)
embedded_operand_list::iterator operand_iterator
EmbeddedMachineOperand & back()
virtual const char * get_name() const
bool is_MachineOperand() const
bool is_stackslot() const
std::size_t op_size() const
virtual const char * get_name() const
virtual OStream & print(OStream &OS) const
virtual IdentifyTy id_base() const
OperandID get_OperandID() const
static unsigned vreg_counter
virtual ManagedStackSlot * to_ManagedStackSlot()
virtual OStream & print(OStream &OS) const
Custom new/delete handler mixin.
const_operand_iterator end() const
bool aquivalence_less(const MachineOperand &MO) const
virtual Register * to_Register()
bool is_StackSlot() const
virtual ~MachineOperand()
virtual ManagedStackSlot * to_ManagedStackSlot()
Conversion method.
Descriptor of a MachineOperand.
bool operator()(cacao::jit::compiler2::MachineOperand *lhs, cacao::jit::compiler2::MachineOperand *rhs) const
virtual VoidOperand * to_VoidOperand()
virtual UnassignedReg * to_UnassignedReg()
virtual VirtualRegister * to_VirtualRegister()
Register(Type::TypeID type)
virtual OStream & print(OStream &OS) const
Print a human-readable representation of this slot.
virtual const char * get_name() const
alloc::vector< EmbeddedMachineOperand >::type embedded_operand_list
virtual Register * to_Register()
std::list< T, Allocator< T > > type
operand_iterator find(MachineOperand *op)
virtual Address * to_Address()
std::size_t IdentifyOffsetTy
virtual bool is_virtual() const
True if operand is virtual and must be assigned during register allocation.
u4 index
Represents the slot's position in the virtual stack frame.
MachineOperand(OperandID op_id, Type::TypeID type)
std::vector< T, Allocator< T > > type
A "virtual" slot that will eventually be mapped to a machine-level slot.
Simple stream class for formatted output.
virtual VirtualRegister * to_VirtualRegister()
virtual const char * get_name() const
virtual bool is_virtual() const
True if operand is virtual and must be assigned during register allocation.
VirtualRegister(Type::TypeID type)
virtual VoidOperand * to_VoidOperand()
bool has_embedded_operands()
virtual MachineRegister * to_MachineRegister()
alloc::list< MachineOperand * >::type OperandFile
embedded_operand_list::const_iterator const_operand_iterator
StackSlot(int index, Type::TypeID type)
bool is_VoidOperand() const
OStream & operator<<(OStream &OS, const std::string &t)
std::size_t operator()(cacao::jit::compiler2::MachineOperand *v) const
virtual bool needs_allocation() const
Return true if operand is processed during register allocation.
virtual Immediate * to_Immediate()
ManagedStackSlot(StackSlotManager *SSM, Type::TypeID type)
Construct a ManagedStackSlot.
Address(Type::TypeID type)
Construct an Address.
static std::size_t id_counter
bool aquivalent(const MachineOperand &MO) const
StackSlotManager * get_parent() const
std::size_t IdentifySizeTy
Type::TypeID get_type() const
virtual const char * get_name() const
StackSlotManager * parent
The StackSlotManager that created (and owns) this slot.
virtual const char * get_name() const
Operands that can be directly used by the machine (register, memory, stackslot)
EmbeddedMachineOperand(MachineOperand *op)
MachineOperandDesc * real
std::size_t get_id() const
virtual StackSlot * to_StackSlot()
void set_index(unsigned index)
Set the index of the slot.
bool is_ManagedStackSlot() const
virtual IdentifyOffsetTy id_offset() const
bool operator()(MachineOperand *lhs, MachineOperand *rhs) const
embedded_operand_list embedded_operands
TODO describe.
virtual StackSlot * to_StackSlot()
int index
index of the stackslot
virtual Address * to_Address()
const_operand_iterator begin() const
virtual bool needs_allocation() const
Return true if operand is processed during register allocation.
virtual IdentifySizeTy id_size() const
bool is_Immediate() const
virtual MachineOperand * to_MachineOperand()
virtual OStream & print(OStream &OS) const
EmbeddedMachineOperand & front()
virtual const char * get_name() const
virtual UnassignedReg * to_UnassignedReg()
UnassignedReg(Type::TypeID type)