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codegen.hpp
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1 /* src/vm/jit/x86_64/codegen.hpp - code generation macros for x86_64
2 
3  Copyright (C) 1996-2013
4  CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
5 
6  This file is part of CACAO.
7 
8  This program is free software; you can redistribute it and/or
9  modify it under the terms of the GNU General Public License as
10  published by the Free Software Foundation; either version 2, or (at
11  your option) any later version.
12 
13  This program is distributed in the hope that it will be useful, but
14  WITHOUT ANY WARRANTY; without even the implied warranty of
15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16  General Public License for more details.
17 
18  You should have received a copy of the GNU General Public License
19  along with this program; if not, write to the Free Software
20  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21  02110-1301, USA.
22 
23 */
24 
25 
26 #ifndef CODEGEN_HPP_
27 #define CODEGEN_HPP_ 1
28 
29 #include "config.h"
30 
31 #include <ucontext.h>
32 
33 #include "vm/types.hpp"
34 
35 #include "vm/jit/x86_64/emit.hpp"
36 
37 /* additional functions and macros to generate code ***************************/
38 
39 /* MCODECHECK(icnt) */
40 
41 #define MCODECHECK(icnt) \
42  do { \
43  if ((cd->mcodeptr + (icnt)) > cd->mcodeend) \
44  codegen_increase(cd); \
45  } while (0)
46 
47 
48 #define ALIGNCODENOP \
49  do { \
50  int len = (-(ptrint) cd->mcodeptr) & 7; \
51  if (len) \
52  emit_nop(cd, len); \
53  } while (0)
54 
55 
56 #define PATCH_ALIGNMENT(addr, offset, size) \
57  ((((addr)+(offset)+(size)-1) & ~((size)-1)) - ((addr)+(offset)))
58 
59 
60 #define ICONST(r,c) \
61  do { \
62  if ((c) == 0) \
63  M_CLR((d)); \
64  else \
65  M_IMOV_IMM((c), (d)); \
66  } while (0)
67 /* do { \ */
68 /* M_IMOV_IMM((c), (d)); \ */
69 /* } while (0) */
70 
71 
72 #define LCONST(r,c) \
73  do { \
74  if ((c) == 0) \
75  M_CLR((d)); \
76  else \
77  M_MOV_IMM((c), (d)); \
78  } while (0)
79 
80 
81 /* branch defines *************************************************************/
82 
83 #define BRANCH_UNCONDITIONAL_SIZE 5 /* size in bytes of a branch */
84 #define BRANCH_CONDITIONAL_SIZE 6 /* size in bytes of a branch */
85 
86 /* These NOPs are never executed; they are only used as placeholders during
87  * code generation.
88  */
89 #define BRANCH_NOPS \
90  do { \
91  M_NOP; \
92  M_NOP; \
93  M_NOP; \
94  M_NOP; \
95  M_NOP; \
96  M_NOP; \
97  } while (0)
98 
99 
100 /* patcher defines ************************************************************/
101 
102 #define PATCHER_CALL_SIZE 2 /* size in bytes of a patcher call */
103 
104 #define PATCHER_NOPS \
105  do { \
106  emit_nop(cd, 2); \
107  } while (0)
108 
109 
110 /* macros to create code ******************************************************/
111 
112 #define M_BYTE1(a) \
113  do { \
114  *(cd->mcodeptr) = (a); \
115  cd->mcodeptr++; \
116  } while (0)
117 
118 
119 #define M_BYTE2(a, b) \
120  do { \
121  M_BYTE1(a); \
122  M_BYTE1(b); \
123  } while (0)
124 
125 
126 #define M_MOV(a,b) emit_mov_reg_reg(cd, (a), (b))
127 #define M_MOV_IMM(a,b) emit_mov_imm_reg(cd, (u8) (a), (b))
128 
129 #define M_IMOV(a,b) emit_movl_reg_reg(cd, (a), (b))
130 #define M_IMOV_IMM(a,b) emit_movl_imm_reg(cd, (u4) (a), (b))
131 
132 #define M_FMOV(a,b) emit_movq_reg_reg(cd, (a), (b))
133 #define M_DMOV(a,b) M_FMOV(a,b)
134 
135 #define M_ILD(a,b,disp) emit_movl_membase_reg(cd, (b), (disp), (a))
136 #define M_LLD(a,b,disp) emit_mov_membase_reg(cd, (b), (disp), (a))
137 
138 #define M_ILD32(a,b,disp) emit_movl_membase32_reg(cd, (b), (disp), (a))
139 #define M_LLD32(a,b,disp) emit_mov_membase32_reg(cd, (b), (disp), (a))
140 
141 #define M_IST(a,b,disp) emit_movl_reg_membase(cd, (a), (b), (disp))
142 #define M_LST(a,b,disp) emit_mov_reg_membase(cd, (a), (b), (disp))
143 
144 #define M_IST_IMM(a,b,disp) emit_movl_imm_membase(cd, (a), (b), (disp))
145 #define M_LST_IMM32(a,b,disp) emit_mov_imm_membase(cd, (a), (b), (disp))
146 
147 #define M_IST32(a,b,disp) emit_movl_reg_membase32(cd, (a), (b), (disp))
148 #define M_LST32(a,b,disp) emit_mov_reg_membase32(cd, (a), (b), (disp))
149 
150 #define M_IST32_IMM(a,b,disp) emit_movl_imm_membase32(cd, (a), (b), (disp))
151 #define M_LST32_IMM32(a,b,disp) emit_mov_imm_membase32(cd, (a), (b), (disp))
152 
153 #define M_IADD(a,b) emit_alul_reg_reg(cd, ALU_ADD, (a), (b))
154 #define M_ISUB(a,b) emit_alul_reg_reg(cd, ALU_SUB, (a), (b))
155 #define M_IMUL(a,b) emit_imull_reg_reg(cd, (a), (b))
156 
157 #define M_IADD_IMM(a,b) emit_alul_imm_reg(cd, ALU_ADD, (a), (b))
158 #define M_ISUB_IMM(a,b) emit_alul_imm_reg(cd, ALU_SUB, (a), (b))
159 #define M_IMUL_IMM(a,b,c) emit_imull_imm_reg_reg(cd, (b), (a), (c))
160 
161 #define M_ISUB_IMM_MEMBASE(a,b,c,lock) emit_alul_imm_membase(cd, ALU_SUB, (a), (b), (c), (lock))
162 
163 #define M_LADD(a,b) emit_alu_reg_reg(cd, ALU_ADD, (a), (b))
164 #define M_LSUB(a,b) emit_alu_reg_reg(cd, ALU_SUB, (a), (b))
165 #define M_LMUL(a,b) emit_imul_reg_reg(cd, (a), (b))
166 
167 #define M_LADD_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADD, (a), (b))
168 #define M_LSUB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SUB, (a), (b))
169 #define M_LMUL_IMM(a,b,c) emit_imul_imm_reg_reg(cd, (b), (a), (c))
170 
171 #define M_IINC(a) emit_incl_reg(cd, (a))
172 #define M_LINC(a) emit_incq_reg(cd, (a))
173 #define M_IDEC(a) emit_decl_reg(cd, (a))
174 
175 #define M_ALD(a,b,disp) \
176  do { \
177  if (b == RIP) \
178  M_LLD(a, b, disp + -((cd->mcodeptr + 7) - cd->mcodebase)); \
179  else \
180  M_LLD(a, b, disp); \
181  } while (0)
182 
183 #define M_ALD32(a,b,disp) M_LLD32(a,b,disp)
184 #define M_ALD_DSEG(a,disp) M_ALD(a,RIP,disp)
185 
186 #define M_ALD_MEM(a,disp) emit_mov_mem_reg(cd, (disp), (a))
187 
188 #define M_ALD_MEM_GET_OPC(p) ( *( (p) + 1))
189 #define M_ALD_MEM_GET_MOD(p) (((*( (p) + 2)) >> 6) & 0x03)
190 #define M_ALD_MEM_GET_REG(p) ((((*( (p) + 2)) >> 3) & 0x07) + (((*(p) >> 2) & 0x01) << 3))
191 #define M_ALD_MEM_GET_RM(p) (((*( (p) + 2)) ) & 0x07)
192 #define M_ALD_MEM_GET_DISP(p) ( *((u4 *) ((p) + 4)))
193 
194 #define M_AST(a,b,c) M_LST(a,b,c)
195 #define M_AST_IMM32(a,b,c) M_LST_IMM32(a,b,c)
196 
197 #define M_AADD(a,b) M_LADD(a,b)
198 #define M_AADD_IMM(a,b) M_LADD_IMM(a,b)
199 #define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b)
200 
201 #define M_ISUB_IMM32(a,b) emit_alul_imm32_reg(cd, ALU_SUB, (a), (b))
202 
203 #define M_LADD_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_ADD, (a), (b))
204 #define M_LSUB_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_SUB, (a), (b))
205 
206 #define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b)
207 
208 #define M_ILEA(a,b,c) emit_leal_membase_reg(cd, (a), (b), (c))
209 #define M_LLEA(a,b,c) emit_lea_membase_reg(cd, (a), (b), (c))
210 #define M_ALEA(a,b,c) M_LLEA(a,b,c)
211 
212 #define M_INEG(a) emit_negl_reg(cd, (a))
213 #define M_LNEG(a) emit_neg_reg(cd, (a))
214 
215 #define M_IAND(a,b) emit_alul_reg_reg(cd, ALU_AND, (a), (b))
216 #define M_IOR(a,b) emit_alul_reg_reg(cd, ALU_OR, (a), (b))
217 #define M_IXOR(a,b) emit_alul_reg_reg(cd, ALU_XOR, (a), (b))
218 
219 #define M_IAND_IMM(a,b) emit_alul_imm_reg(cd, ALU_AND, (a), (b))
220 #define M_IOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_OR, (a), (b))
221 #define M_IXOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_XOR, (a), (b))
222 
223 #define M_LAND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b))
224 #define M_LOR(a,b) emit_alu_reg_reg(cd, ALU_OR, (a), (b))
225 #define M_LXOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
226 
227 #define M_LAND_IMM(a,b) emit_alu_imm_reg(cd, ALU_AND, (a), (b))
228 #define M_LOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_OR, (a), (b))
229 #define M_LXOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_XOR, (a), (b))
230 
231 #define M_BSEXT(a,b) emit_movsbq_reg_reg(cd, (a), (b))
232 #define M_SSEXT(a,b) emit_movswq_reg_reg(cd, (a), (b))
233 #define M_ISEXT(a,b) emit_movslq_reg_reg(cd, (a), (b))
234 
235 #define M_BZEXT(a,b) emit_movzbq_reg_reg(cd, (a), (b))
236 #define M_CZEXT(a,b) emit_movzwq_reg_reg(cd, (a), (b))
237 
238 #define M_ISLL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHL, (a), (b))
239 #define M_ISRA_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SAR, (a), (b))
240 #define M_ISRL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHR, (a), (b))
241 
242 #define M_LSLL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b))
243 #define M_LSRA_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b))
244 #define M_LSRL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b))
245 
246 #define M_TEST(a) emit_test_reg_reg(cd, (a), (a))
247 #define M_ITEST(a) emit_testl_reg_reg(cd, (a), (a))
248 
249 #define M_LCMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
250 #define M_LCMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
251 #define M_LCMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
252 #define M_LCMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
253 #define M_LCMP_MEMINDEX(a,b,c,d,e) emit_alul_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e))
254 
255 #define M_ICMP(a,b) emit_alul_reg_reg(cd, ALU_CMP, (a), (b))
256 #define M_ICMP_IMM(a,b) emit_alul_imm_reg(cd, ALU_CMP, (a), (b))
257 #define M_ICMP_IMM32(a,b) emit_alul_imm32_reg(cd, ALU_CMP, (a), (b))
258 #define M_ICMP_IMM_MEMBASE(a,b,c) emit_alul_imm_membase(cd, ALU_CMP, (a), (b), (c))
259 #define M_ICMP_MEMBASE(a,b,c) emit_alul_membase_reg(cd, ALU_CMP, (a), (b), (c))
260 #define M_ICMP_MEMINDEX(a,b,c,d,e) emit_alu_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e))
261 
262 #define M_ACMP(a,b) M_LCMP(a,b)
263 
264 #define M_BEQ(disp) emit_jcc(cd, CC_E, (disp))
265 #define M_BNE(disp) emit_jcc(cd, CC_NE, (disp))
266 #define M_BLT(disp) emit_jcc(cd, CC_L, (disp))
267 #define M_BLE(disp) emit_jcc(cd, CC_LE, (disp))
268 #define M_BGE(disp) emit_jcc(cd, CC_GE, (disp))
269 #define M_BGT(disp) emit_jcc(cd, CC_G, (disp))
270 
271 #define M_BNS(a) emit_jcc(cd, CC_NS, (a))
272 
273 #define M_BULT(disp) emit_jcc(cd, CC_B, (disp))
274 #define M_BULE(disp) emit_jcc(cd, CC_BE, (disp))
275 #define M_BUGE(disp) emit_jcc(cd, CC_AE, (disp))
276 #define M_BUGT(disp) emit_jcc(cd, CC_A, (disp))
277 
278 #define M_SETE(a) emit_setcc_reg(cd, CC_E, (a))
279 #define M_SETNE(a) emit_setcc_reg(cd, CC_NE, (a))
280 #define M_SETULE(a) emit_setcc_reg(cd, CC_BE, (a))
281 
282 #define M_CMOVEQ(a,b) emit_cmovcc_reg_reg(cd, CC_E, (a), (b))
283 #define M_CMOVNE(a,b) emit_cmovcc_reg_reg(cd, CC_NE, (a), (b))
284 #define M_CMOVLT(a,b) emit_cmovcc_reg_reg(cd, CC_L, (a), (b))
285 #define M_CMOVLE(a,b) emit_cmovcc_reg_reg(cd, CC_LE, (a), (b))
286 #define M_CMOVGE(a,b) emit_cmovcc_reg_reg(cd, CC_GE, (a), (b))
287 #define M_CMOVGT(a,b) emit_cmovcc_reg_reg(cd, CC_G, (a), (b))
288 
289 #define M_CMOVULT(a,b) emit_cmovcc_reg_reg(cd, CC_B, (a), (b))
290 #define M_CMOVUGT(a,b) emit_cmovcc_reg_reg(cd, CC_A, (a), (b))
291 #define M_CMOVP(a,b) emit_cmovcc_reg_reg(cd, CC_P, (a), (b))
292 
293 #define M_PUSH(a) emit_push_reg(cd, (a))
294 #define M_PUSH_IMM(a) emit_push_imm(cd, (a))
295 #define M_POP(a) emit_pop_reg(cd, (a))
296 
297 #define M_JMP(a) emit_jmp_reg(cd, (a))
298 #define M_JMP_IMM(a) emit_jmp_imm(cd, (a))
299 #define M_JMP_IMM2(a) emit_jmp_imm2(cd, (a))
300 #define M_CALL(a) emit_call_reg(cd, (a))
301 #define M_CALL_IMM(a) emit_call_imm(cd, (a))
302 #define M_RET M_BYTE1(0xc3)
303 
304 #define M_NOP M_BYTE1(0x90)
305 #define M_UD2 M_BYTE2(0x0f, 0x0b)
306 
307 #define M_CLR(a) M_LXOR(a,a)
308 
309 
310 #define M_FLD(a,b,disp) emit_movss_membase_reg(cd, (b), (disp), (a))
311 #define M_DLD(a,b,disp) emit_movsd_membase_reg(cd, (b), (disp), (a))
312 
313 #define M_FLD32(a,b,disp) emit_movss_membase32_reg(cd, (b), (disp), (a))
314 #define M_DLD32(a,b,disp) emit_movsd_membase32_reg(cd, (b), (disp), (a))
315 
316 #define M_FST(a,b,disp) emit_movss_reg_membase(cd, (a), (b), (disp))
317 #define M_DST(a,b,disp) emit_movsd_reg_membase(cd, (a), (b), (disp))
318 
319 #define M_FST32(a,b,disp) emit_movss_reg_membase32(cd, (a), (b), (disp))
320 #define M_DST32(a,b,disp) emit_movsd_reg_membase32(cd, (a), (b), (disp))
321 
322 #define M_FADD(a,b) emit_addss_reg_reg(cd, (a), (b))
323 #define M_DADD(a,b) emit_addsd_reg_reg(cd, (a), (b))
324 #define M_FSUB(a,b) emit_subss_reg_reg(cd, (a), (b))
325 #define M_DSUB(a,b) emit_subsd_reg_reg(cd, (a), (b))
326 #define M_FMUL(a,b) emit_mulss_reg_reg(cd, (a), (b))
327 #define M_DMUL(a,b) emit_mulsd_reg_reg(cd, (a), (b))
328 #define M_FDIV(a,b) emit_divss_reg_reg(cd, (a), (b))
329 #define M_DDIV(a,b) emit_divsd_reg_reg(cd, (a), (b))
330 
331 #define M_CVTIF(a,b) emit_cvtsi2ss_reg_reg(cd, (a), (b))
332 #define M_CVTID(a,b) emit_cvtsi2sd_reg_reg(cd, (a), (b))
333 #define M_CVTLF(a,b) emit_cvtsi2ssq_reg_reg(cd, (a), (b))
334 #define M_CVTLD(a,b) emit_cvtsi2sdq_reg_reg(cd, (a), (b))
335 #define M_CVTFI(a,b) emit_cvttss2si_reg_reg(cd, (a), (b))
336 #define M_CVTDI(a,b) emit_cvttsd2si_reg_reg(cd, (a), (b))
337 #define M_CVTFL(a,b) emit_cvttss2siq_reg_reg(cd, (a), (b))
338 #define M_CVTDL(a,b) emit_cvttsd2siq_reg_reg(cd, (a), (b))
339 
340 #define M_CVTFD(a,b) emit_cvtss2sd_reg_reg(cd, (a), (b))
341 #define M_CVTDF(a,b) emit_cvtsd2ss_reg_reg(cd, (a), (b))
342 
343 
344 /* system instructions ********************************************************/
345 
346 #define M_MFENCE emit_mfence(cd)
347 #define M_RDTSC emit_rdtsc(cd)
348 
349 #define M_IINC_MEMBASE(a,b) emit_incl_membase(cd, (a), (b))
350 #define M_LINC_MEMBASE(a,b) emit_incq_membase(cd, (a), (b))
351 
352 #define M_IDEC_MEMBASE(a,b) emit_decl_membase(cd, (a), (b))
353 
354 #define M_IADD_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADD, (a), (b), (c))
355 #define M_IADC_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADC, (a), (b), (c))
356 #define M_ISUB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SUB, (a), (b), (c))
357 #define M_ISBB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SBB, (a), (b), (c))
358 
359 
360 #endif // CODEGEN_HPP_
361 
362 /*
363  * These are local overrides for various environment variables in Emacs.
364  * Please do not remove this and leave it at the end of the file, where
365  * Emacs will automagically detect them.
366  * ---------------------------------------------------------------------
367  * Local variables:
368  * mode: c++
369  * indent-tabs-mode: t
370  * c-basic-offset: 4
371  * tab-width: 4
372  * End:
373  * vim:noexpandtab:sw=4:ts=4:
374  */
emit.hpp
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